1. Field
The present embodiment relates to solid-state image pickup devices and image pickup methods, and particularly to a solid-state image pickup device using an analog-to-digital converter disposed for each column in a pixel array and an image pickup method using the solid-state image pickup device.
2. Description of the Related Art
There are known solid-state image pickup devices, such as complementary metal-oxide semiconductor (CMOS) image sensors, that incorporate so-called column ADC circuits, that is, analog-to-digital converter circuits disposed for individual columns of a pixel array.
FIG. 8 is a diagram showing the structure of a conventional solid-state image pickup device 500 incorporating column ADC circuits.
The conventional solid-state image pickup device 500 includes a pixel array 501, a readout circuit block 502, a column ADC circuit block 503, a latch/serial-parallel conversion circuit 504, a digital-to-analog converter (DAC) circuit 505, a comparator 506, a timing generation circuit 507, and a ramp signal generation circuit 508.
The pixel array 501 includes a light-receiving pixel area 501a including a plurality of light-receiving pixel elements (not shown) disposed in a matrix manner and a light-blocking pixel area 501b including a plurality of light-blocking pixel elements (not shown). A pixel signal read from a light-blocking pixel element is used to eliminate an offset owing to a dark current component, from a pixel signal of a light-receiving pixel element. The light-blocking pixel area 501b is disposed to surround the light-receiving pixel area 501a, for instance.
The readout circuit block 502 reads pixel signals of each read line (horizontal line) from the pixel array 501. The readout circuit block 502 includes a column amplifier circuit block 502a for amplifying the read pixel signals and a column correlated double sampling (CDS) circuit block 502b for reducing noise. The column amplifier circuit block 502a includes amplifier circuits disposed for individual columns. The column CDS circuit block 502b includes CDS circuits disposed for individual columns.
The column ADC circuit block 503 includes ADC circuits disposed for individual columns and converts analog pixel signals read by the readout circuit block 502 to digital values.
The latch/serial-parallel conversion circuit 504 latches the digital values of the pixel signals obtained by the column ADC circuit block 503, performs serial-to-parallel conversion, and outputs parallel data.
The DAC circuit 505 performs digital-to-analog conversion of a pixel signal read from a light-blocking pixel element, of the pixel signals output from the latch/serial-parallel conversion circuit 504, and obtains a voltage value (black level).
The comparator 506 compares the black level output from the DAC circuit 505 and a reference voltage VREF, which is an ideal black level of the readout circuit block 502 and the column ADC circuit block 503, and adjusts, in accordance with the difference therebetween, a reference voltage VREFa to be supplied to the readout circuit block 502.
The timing generation circuit 507 generates timing signals and gives the signals to the readout circuit block 502, the column ADC circuit block 503, the latch/serial-parallel conversion circuit 504, the DAC circuit 505, and the ramp signal generation circuit 508.
The ramp signal generation circuit 508 includes an amplifier circuit 5081, a constant-current power supply 5082, a switch S10, and a capacitor C10. The amplifier circuit 5081 has one input terminal to receive the reference voltage VREF and the other input terminal connected to its output terminal, and functions as a buffer. The output terminal of the amplifier circuit 5081 is connected through the switch S10 to one terminal of the capacitor C10 and one terminal of the constant-current power supply 5082. The other terminals of the capacitor C10 and the constant-current power supply 5082 are grounded.
In the ramp signal generation circuit 508, when the switch S10 is turned on by a timing signal sent from the timing generation circuit 507, the capacitor C10 retains the reference voltage VREF. When the switch S10 is turned off later, a ramp waveform increasing at a constant ratio with reference to the reference voltage VREF is output from the one terminal of the constant-current power supply 5082 and input to the column ADC circuit block 503.
FIG. 9 is a diagram showing the structure of a conventional column CDS circuit.
The figure shows a column CDS circuit 510 disposed for a single column, in the column CDS circuit block 502b. 
The column CDS circuit 510 includes amplifier circuits 511 and 512, switches S11 and S12, and capacitors C11 and C12. The amplifier circuit 511 has one input terminal to receive a pixel signal output from the column amplifier circuit block 502a through the switch S11. The capacitor C11 has one terminal connected between the switch S11 and the input terminal of the amplifier circuit 511 and another terminal grounded. The amplifier circuit 511 has another input terminal connected to its output terminal and functions as a buffer.
The amplifier circuit 512 has one input terminal connected through the capacitor C12 to the output terminal of the amplifier circuit 511. The reference voltage VREFa is applied through the switch S12 between the capacitor C12 and the input terminal of the amplifier circuit 512. The amplifier circuit 512 has another input terminal connected to its output terminal and functions as a buffer. The output terminal of the amplifier circuit 512 is connected to the column ADC circuit block 503.
In the column CDS circuit 510, described above, when the switches S11 and S12 are turned on by timing signals from the timing generation circuit 507, the capacitor C12 retains a reset signal (noise) read at a reset of a pixel element (photodiode), as a voltage value with reference to the reference voltage VREFa. When the timing signal turns off the switch S12, the signal charge accumulated in accordance with the integral time (exposure time) is retained in the capacitor C11 through the column amplifier circuit block 502a, as the pixel signal. By subtracting the voltage value retained in the capacitor C12 from the pixel signal, which includes a noise component, the noise component is eliminated from the pixel signal. Then, the amplifier circuit 512 outputs the sum of the noise-eliminated pixel signal and the reference voltage VREFa.
FIG. 10 shows pixel signals and ranges of AD conversion in a read operation in the conventional solid-state image pickup device.
The figure shows pixel signals read from pixel elements in consecutive horizontal lines H1 and H2 of the pixel array 501 shown in FIG. 8. The upper chart shows pixel signals input to the readout circuit block 502, and the lower chart shows pixel signals input to the column ADC circuit block 503.
In the readout period for the horizontal line H1, pixel signals are input to the readout circuit block 502, when viewed from the left of the line in FIG. 8, from the light-blocking pixel area 501b, from the light-receiving pixel area 501a, and from the light-blocking pixel area 501b again. The pixel signals from these areas are input simultaneously in parallel, in accordance with a timing signal. After a blanking (BK) period, pixel signals of the next horizontal line H2 are input to the readout circuit block 502 in the same manner.
The pixel signals amplified and noise-eliminated by the readout circuit block 502 is input to the column ADC circuit block 503 (lower chart in FIG. 10). The pixel signals of the horizontal line H1 input to the column ADC circuit block 503 are subjected to analog-to-digital conversion based on the ramp signal with reference to the reference voltage VREF, latched by the latch/serial-parallel conversion circuit 504, and output as parallel data. In this process, pixel signals from the light-blocking pixel area 501b are converted to analog voltage values (black levels) by the DAC circuit 505 and compared with the reference voltage VREF by the comparator 506. In the example shown in FIG. 10, the average black level Vba1 of the horizontal line H1 is lower than the reference voltage VREF. The comparator 506 accordingly inputs a reference voltage VREFa2 obtained by adding the offset of the horizontal line H1 to the reference voltage VREFa1, to the readout circuit block 502.
As has been described above, the conventional solid-state image pickup device 500 tries to eliminate the dark current component by adjusting the black level through the adjustment of the reference voltage VREFa of the readout circuit block 502 by using the pixel signals of the light-blocking pixel elements after AD conversion (Japanese Unexamined Patent Publication No. 2005-101985).
However, the dark current component varies among horizontal lines. A difference between the offset of the immediately-preceding horizontal line and the offset of the pixel signal of the currently read horizontal line makes it impossible to adjust the black level completely.
In the example shown in FIG. 10, for example, although the average black level Vba2 of the pixel signals of the horizontal line H2 input to the readout circuit block 502 equals the reference voltage VREF, the black level is adjusted in accordance with the offset of the horizontal line H1. This generates an offset in the horizontal line H2, producing horizontal stripes in the output image.
The remaining offset reduces the number of quantization levels of actual data accordingly in AD conversion, as shown in FIG. 10, lowering the resolution, and the lowered resolution results in degraded image quality.